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MOTOROLA 


ASYNCHRONOUS COMMUNICATIONS INTERFACE 
ADAPTER (ACIA) 

The MC6850 Asynchronous Communications Interface Adapter pro- 
vides the data formatting and control to interface serial asynchronous 
data communications information to bus organized systems such as the 
MC6800 Mtcroprocessrng Unit. 

The bus interface of the MC6850 includes select, enable, read/write, 
interrupt and bus interface logic to allow data transfer over an 8-bit 
bidirectional data bus. The parallel data of the bus system is serially 
transmitted and received by the asynchronous data interface, with pro 
per formatting and error checking The functional configuration of the 
ACIA is programmed via the data bus during system initialization A 
programmable Control Register provides variable word lengths, clock 
division ratios, transmit control, receive control, and interrupt control. 
For peripheral or modem operation, three control lines are provided. 
These lines allow the ACIA to interface directly with the MC6860L 
0-600 bps digital modem 

• 8 and 9 Bit Transmission 

• Optional Even and Odd Parity 

• Parity, Overrun and Framing Error Checking 

• Programmable Control Register 

• Optional - 1, 16, and -64 Clock Modes 

• Up to 1.0 Mbps Transmission 

• False Start Bit Deletion 

• Peripheral/ Modem Control Functions 

• Double Buffered 

• One- or Two-Stop Bit Operation 


MOS 

IN CHANNEL. SILICON-GATE) 

ASYNCHRONOUS 
COMMUNICATIONS INTERFACE 
ADAPTER 


S SUFFIX 

UR DIP PACKAGE 
CASE 62'3 





P SUFFIX 
PLASTIC PACKAGE 


L SUFFIX 
CERAMIC PACKAGE 
CASE 716 


MC66S0 ASYNCHRONOUS COMMUNICATIONS INTERFACE ADAPTER 
BLOCK DIAGRAM 



P«f iph«f»l/ 
Modem 
Control 



4-527 











MC6850MC68A50MC68B50 


MAXIMUM RATINGS 


Characteristics 


Value 


Supply Voltage 

■ ■ 


wm 

Input Voltage 


HAlMdEEB 


Operating Temperature Range 
MC6850, MC68A50, MC68B50 
MC6850C. MC68A50C. MC68850C 

r A 

t l «o T H 
0 to 70 
-40 to +85 

°c 

Storage Temperature Range 

T stq 

- 55 to + 150 

~c 


THERMAL CHARACTERISTICS 


Characteristic 

Symbol 

Value 

Unit 

Thermal Resistance 
Plastic 
Ceramic 
Cerdip 

®JA 

120 

60 

65 

°C/W 


This device contains circuitry to protect the 
inputs against damage due to high static 
voltages or electric fields, however, it ts ad 
vised that normal precautions be taken to 
avoid application of any voltage highei than 
maximum rated voltages to this high 
impedance circuit Reliability of operation is 
enhanced if unused inputs are tied to an ap 
prepnale logic voltage level fe g , either Vcc 
or V cc > 


(1) 


POWER CONSIDERATIONS 

The average chipjunction temperature, Tj. in X can be obtained from: 

Tj = Ta + IPd*#JA> 

Where: 

Ta" A mbient Temperature, °C 

®JA“ Package Thermal Resistance. Junction-to-Ambient. x/W 
P D"P|NT+PP0RT 

p INT"ICC*Vcc, Watts - Chip Internal Power 
PpORT"Port Power Dissipation, Watts - User Determined 

For most applications PpORT-« P|NT and can be neglected P P0 R T may become significant if the device is conhguted to 
drive Darlington bases or sink LED loads. 

An approximate relationship between Pq and Tj (if PpoRT is neglectedl is 

p D=K-(Tj + 273"C) (2) 

Solving equations 1 and 2 for K gives: 

K = P D *(Ta + 273X1 + *ja«Pd 2 ,3, 

Where K is a constant pertaining to the particular part K can be determined from equation 3 bv measuring Pn lai equilibrium! 
valuVorTA TA USn9 ,hS ValUe 0f K ' he V0lUBS ol p D and Tj can be obtained by solving equations It I and (2) iteratively for any 


DC ELECTRICAL CHARACTERISTICS IVcc»50 Vdc ±5%. Vss = 0 Ta = Tl to Th unless otherwise noted I 


Characteristic 

Symbol 

Min 

Typ 

Max 

Unit 

Input High Voltage 

V|H 

Vss + 2.0 



V 

Input Low Voltage 

V)L 

Vss-0.3 

- 

Vss+0 8 

V 

input Leakage Current 

R/W, CS0, CS1, CSZ. Enable 






(Vj n =0 to 5.25 V) 

RS. Rx O, Rx C, CT5, DCD 

'in 

“ 

1.0 

2.6 

xA 

Three-State (Off State) Input Current 

CXTD7 






IVin-0.4 to 2 4 VI 


•tsi 

“ 

20 

10 

X A 

Output High Voltage 

00-D7 









V$s+24 





TxOata, RTS 


Vss+24 

H 




VOL 

- 



V 

Output Leakage Current (Off State) (Vqh = 2.4 VI 



- 

■H 


■SB 

Internal Power Dissipation (Measured at T = T|_) 

HIM 

- 

ESI 

525 


Internal Input Capacitance 







IVjn « 0. Ta * 26X. 1 » t .0 MHz) 

D0-D7 


_ 

§■ 

12.5 


E.Tx CLK, Rx CLK, R/W. RS. RxData, CS0.CS1.TO. CTS.D^D 


- 


7,5 


Output Capacitance 

RTS, Tx Data 



— 



IV in » 0, T A - 25X, f = 1 .0 MHz) 

ITO 

c out 

- 


50 

P F 


4-528 











MC6850* M C68A50* MC68B50 


SERIAL DATA TIMING CHARACTERISTICS 


Characteristic 





■pa 


irai 

IT?TB 

ITW 

Era 

ITWl 

irei 


Data Clock Pulse Width, Low 

* 16. - 64 Modes 


600 

_ 

450 

wm 


B 


(See Figure 1) 

♦ 1 Mode 


900 

- 

660 

m 

El 

B 


Data Clock Pulse Width, High 

*16. *64 Modes 


600 

- 

450 


E3 

_ 


(See Figure 21 

1 Mode 


900 

- 

660 

B 


- 


Data Clock Frequency 

♦ 16, +64 Modes 


- 

0.8 

- 



IB 



+ 1 Mode 


- 


_ 



itfrol 


Data Clock-to-Data Delay for Transmitter ISee Figure 3) 

EB 

- 

ESI 

- 

3 


c 

wm 

Receive Data Setup Time (See Figure 4) 

♦ 1 Mode 

BESS 

EM 

IEj 

E3 


o 



Receive Data Hold Time (See Figure 5) 

+ 1 Mode 

BliMll 

KSt 

- 

Ea 

- 

EH 

- 


Interrupt Request Release Time (See Figure 6) 

■ 

- 

KO 

- 

IftCT 


EB 

wm 

Request- to Send Delay Time (See Figure 6) 


- 

e a 

_ 

da 

- 

E3 

wm 

Input Rise and Fatl Times (or 10% of the pulse width if smaller! 

— 

- 

■El 

- 

KOI 

- 

EQI 

wm 


FIGURE 1 - CLOCK PULSE WtOTM. LOW-STATE 


T* Clk 
or 

R> Ctk 



FIGURE 2 - CLOCK PULSE WIDTH, HIGH-STATE 



L pw c „ *1 


FIGURE 3 - TRANSMIT DATA OUTPUT DELAY 


'■ m ~ \ / 



FIGURE 4 - RECEIVE DATA SETUP TIME 
(-*-1 Mod*) 



FIGURE 5 - RECEIVE DATA HOLD TIME 
(-1 Mode) 



FIGURE 6 - REQUEST TO SEND DELAY AND 
INTERRUPT REQUEST RELEASE TIMES 



Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted 


4-529 













MC6850* MC68A50* MC68B50 


BUS TIMING CHARACTERISTICS (See Notes 1 and 2 and Figure 7) 


Went. 

Number 

Characteristic 

Symbol 



■SH’.KAl 

Unh 

cal 

ca 

i^na 

mi 

03 


1 


K^9 

m 

m 


o 

m 

mm 

4 * 

2 


■239 

Kj| 

|^j| 

Ka 

123 

Kiil 

123 

bib 

3 

Pulse Width. E High 

12331 



Ka 




KB 

4 

Clock Rise and Fall Time 

— 

IB 

El 


d 

Bl 

El 


9 

Address Hold Time 

■ 

KB 

- 



■H 


mm 

13 

Address Setup Time Before E 

B 

80 

- 

El 

- 

■a 

~ 

■SB 

14 

Chip Select Setup Time Before E 


■a 

- 

El 


■a 


ns 

15 

Chip Select Hold Time 

■ 

KM 

- 

K| 

- 

■a 

- 

mm 

10 



E3 

Ka 

El 

Ka 

El: 

Ea 


21 

Write Data Hold Time 


m 


Eli 


■El 


S3 

30 

Output Data Delay Time 


- 



3 



m 

3l 



ca 

- 





mm 


FIGURE 7 - BUS TIMING CHARACTERISTICS 



FIGURE 8 - BUS TIMING TEST LOADS 

Load A 



Load B 
(IRQ Oidyl 


5.0 V 
: 3k0 


C - 130 l O ' DO D 7 

“ 30 ijF tor RTS am! T x Data 


R - 11.7 kll f or DO 07 

- 24 kil for RTS and Tx Data 


4-530 









MC6850*MC68A50*MC68B50 


FIGURE 9 - EXPANDED BLOCK DIAGRAM 


Tr*n*mit Clock 4 
Enable 14 

Read/Writ# 13 
Chip Select 0 8 
Chip Select 1 10 
Chip Select 2 9 
Reflitter Select 1 1 


DO 22 
D1 21 
02 20 

03 19 

04 18 

05 17 
D6 16 
D7 15 


Receive Clock 3 



6 Trentmit Date 


24 Clear to Send 


7 Interrupt Request 
23 Data Carrier Detect 


5 Request to Send 


2 Receive Data 


DEVICE OPERATION 

At the bus interface, the ACIA appears as two addressable 
memory locations. Internally, there are four registers: two 
read only and two write-onty registers. The read-only 
registers are Status and Receive Data; the write-only 
registers are Control and Transmit Data. The serial interface 
consists of serial input and output lines with independent 
docks, and three peripheral/modem control lines. 

POWER ON/MASTER RESET 

The master reset (CRO, CR1) should be set during system 
initialization to insure the reset condition and prepare for pro- 
gramming the ACIA functional configuration when thecom- 
municatio ns c hann el is required. During the first master 
reset, the IRQ and RTS outpu ts are held at level 1. On all 
other master resets, the RTS output car be programmed 
high or low with the IRQ output held high. Control bits CR5 
and CR6 should also be programmed to define the state of 
RTS whenever master reset is utilized. The ACIA also con- 
tains internal power-on reset logic to detect the power line 
turn-on transition and hold the chip in a reset state to pre- 
vent erroneous output transitions prior to initialization. This 
circuitry depends on clean power turn-on transitions. The 


power-on reset is released by means of the bus-programmed 
master reset which must be applied prior to operating the 
ACIA. After master resetting the ACIA. the programmable 
Control Register can be set for a number of options such as 
variable clock divider ratios, variable word length, one or two 
stop bits, parity (even, odd, or none), etc. 

TRANSMIT 

A typical transmitting sequence consists of reading the 
ACIA Status Register either as a result of an interrupt or in 
the ACIA's turn in a polling sequence A character may be 
written into the Transmit Data Register if the status read 
operation has indicated that the Transmit Data Register is 
empty. This character is transferred to a Shift Register where 
it is serialized and transmitted from the Transmit Data output 
preceded by a start bit and followed by one or two stop bits. 
Internal parity (odd or even! can be optionally added to the 
character and will occur between the last data bit and the 
first stop bit. After the first character is written in the Data 
Register, the Status Register can be read again to check for a 
T'ansmit Data Register Empty condition and current 
peripheral status. If the register is empty, another character 
can be loaded for transmission even though the first 
character is in the process of being transmitted (because of 


4-531 









MC6850«MC68A50*MC68B50 


double buffering). The second character will be automatical- 
ly transferred into the Shift Register whBn the first character 
transmission is completed. This sequence continues until all 
the characters have been transmitted. 

RECEIVE 

Data is received from a peripheral by means of the Receive 
Data input. A divide-by-one clock ratio is provided for an ex- 
ternally synchronized clock I to its data) while the divide 
by- 16 and 64 ratios are provided for internal synchronization. 
Bit synchronization in the divide-by-16 and 64 modes is in- 
itiated by the detection of 8 or 32 low samples on the receive 
line in the divide by 16 and 64 modes respectively. False start 
bit deletion capability insures that a full half bit of a start bit 
has been received before the internal clock is synchronized 
to the bit time. As a character is being received, parity (odd 
or even) will be checked and the error indication will be 
available in the Status Register along with framing error, 
overrun error, and Receive Data Register full. In a typical 
receiving sequence, the Status Register is read to determine 
if a character has been received from a peripheral. If the 
Receiver Data Register is full, the character is placed on the 
8-bit ACIA bus when a Read Data command is received from 
the MPU. When parity has been selected for a 7-bit word (7 
bits plus parity), the receiver strips the parity bit (D/=0) so 
that data alone is transferred to the MPU. This feature 
reduces MPU programming. The Status Register can con- 
tinue to be read to determine when another character is 
available in the Receive Data Register. The receiver is also 
double buffered so that a character can be read from the 
data register as another character is being received in the 
shift register. The above sequence continues until all 
characters have been received. 


INPUT/OUTPUT FUNCTIONS 

ACIA INTERFACE SIGNALS FOR MPU 

The ACIA interfaces to the M6800 MPU with an 8-bit 
bidirectional data bus, three chip select lines, a register select 
line, an interrupt request line, read/write line, and enable 
line. These signals permit the MPU to have complete control 
over the ACIA 

ACIA Bidirectional Data (D0-D7) - The bidirectional data 
lines ID0-D7) allow for data transfer between the ACIA and 
the MPU. The data bus output drivers are three-state devices 
that remain in the high- impedance (off) state except when 
the MPU performs an ACIA read operation. 

ACIA Enable (E) — The Enable signal, E, is a high- 
impedance TTL compatible input that enables the bus in- 
put/output data buffers and clocks data to and from the 
ACIA. This signal will normally be a derivative of the MC6800 
4 > 2 Clock or MC6809 E clock. 

Read /Write (R/W) - The Read /Write line is a high- 
impedance input that is TTL compatible and is used to con- 
trol the direction of data flow through the ACIA’s input/ out- 
put data bus interface. When Read/Write is high (MPU Read 
cycle), ACIA output drivers are turned on and a selected 
register is read When it is low, the ACIA output drivers are 


turned off and the MPU writes into a selected register 
Therefore, the Read/Wnte signal is used to select read-only 
or write-only registers within the ACIA. 

Chip Select (CSO, CS1, CS2) - These three high 
impedance TTL-compatible input lines are used to address 
the ACIA . The ACIA is selected when CSO and CS1 are high 
and CS2 is low. Transfers of data to and from the ACIA are 
then performed under the control of the Enable Signal, 
Read/ Write, and Register Select. 

Register Select (RS) - The Register Select line is a h»gh- 
impedance input that is TTL compatible. A high level is used 
to select the Transmit/ Receive Data Registers and a low 
level the Control/ Status Registers. The Read/ Write signal 
line is used in conjunction with Register Select to select the 
read-only or write-only register in each register pair 

Interrupt Request (IRQ) - Interrupt Request is a TTL- 
compatible, open-drain (no internal pullup), activ e low out- 
put that is used to interrupt the MPU The IRQ output re- 
mains low as long as the cause of the interrupt is present and 
the appropriate interrupt enable within t he A CIA is set The 
JSQ status bit, when high, indicates the IRQ output is in the 
active state. 

Interrupts result from conditions in both the transmitter 
and receiver sections of the ACIA. The transmitter section 
causes an interrupt when the Transmitter Interrupt Enabled 
condition is selected (CR5»CR6), and the Transmit Data 
Register Empty (TORE) status bit is high. The TORE status 
bit indicates the current status of the Transmi tter Data 
Register except when inhibited by Clear-to-Send (CTS) be- 
ing high or the ACIA being maintained in the Reset condi- 
tion. The interrupt is cleared by writing data into the 
Transmit Data Register. The interrupt is masked by disabling 
the T ransmitter Interrupt via CR5 or CR6 or by the loss of 
CTS which inhibits the TORE status bit The Receiver sec- 
tion causes an interrupt when the Receiver Interrupt Enable 
is set and the Receive Data Register Full (RDRF) statu s bit is 
high, an Overrun has occurred, or Data Carrier Detect (DCD) 
has gone high An interrupt resulting from the RDRF status 
bit can be cleared by reading data or re setting the ACIA. In- 
terrupts caused by Overrun or loss of DCD are cleared by 
reading the status register after the error condition has oc- 
curred and then reading the Receive Data Register or reset- 
ting the ACIA. The receiver interrupt is masked by resetting 
the Receiver Interrupt Enable. 

CLOCK INPUTS 

Separate high-impedance TTL-compatible inputs are pro- 
vided for clocking of transmitted and received data. Clock 
frequencies of 1, 16, or 64 times the data rate may be 
selected 

Transmit Clock <Tx CLK) — The Transmit Clock input is 
used for the clocking of transmitted data. The transmitter in- 
itiates data on the negative transition of the clock. 

Receive Clock (Rx CLK) — The Receive Clock input is 
used for synchronization of received data. (In the + 1 mode, 
the dock and data must be synchronized externally.) The 
receiver samples the data on the positive transition of the 
clock. 


4-532 



M C6850* M C68 A50« M C68B50 


SERIAL INPUT/OUTPUT LINES 

Receive Data (Rx Data) - The Receive Data line is a high- 
impedance TTL-compatible input through which data is 
received in a serial format. Synchronization with a clock for 
detection of data is accomplished internally when clock rates 
of 16 or 64 times the bit rate are used 

Transmit Data ITx Data) — The Transmit Data output line 
transfers serial data to a modem or other peripheral. 

PERIPHERAL/MODEM CONTROL 

The ACIA includes several functions that permit limited 
control of a peripheral or modem. The functions included are 
Clear to- Send, Requesl-to Send and Data Carrier Detect. 

Clear-to-Send (CTS) - This high impedance TTL- 
c ompatible input provides automatic control of the transmit- 
ting end of a communications link via the modem Clear to- 
Send active low output by inhibiting the Transmit Data 
Register Empty (TORE) status bit. 

Request-to- Send (RTS) — The Request-to- Send output 
enables the MPU to control a peripheral or modem via the 
data bus. The RTS output corresponds to the state of the 
Control Register bits CR5 a nd CR6 When CR6 = 0 or both 
CR5 and CR6= 1, the RTS output is low (the active state). 
This output can also be used for Data Terminal Ready IDTR). 

Data Carrier Detect (DCD) — This high-impedance TTL- 
compatible input provides automatic control, such as in the 
receiving end of a communications lin k by means of a 
modem Data Carrier Detect output. The DCD input inhibits 
and initializes the receiver section of the ACIA when high A 
low-to-high transition of the Data Carrier Detect initiates an 
interrupt to the MPU to indicate the occurrence of a loss of 
carrier when the Receive Interrupt Enab le bit is set The 
Rx CLK must be running for proper DCD operation. 


ACIA REGISTERS 

The expanded block diagram for the ACIA indicates the in- 
ternal registers on the chip that are used for the status, con- 
trol. receiving, and transmitting of data The content of each 
of the registers is summarized in Table 1. 


TRANSMIT DATA REGISTER (TDR) 

Data is written in the Transmit Data Register during the 
negative transition of the enableJE) when the ACIA has been 
addressed with RS high and R/W low Writing data into the 
register causes the Transmit Data Register Empty bit in the 
Status Register to go low Data can then be transmitted. If 
the transmitter is idling and no character is being transmit- 
ted, then the transfer will take place within 1-bit time of the 
trailing edge of the Write command If a character is being 
transmitted, the new data character will commence as soon 
as the previous character is complete. The transfer of data 
causes the Transmit Data Register Empty (TORE) bit to in- 
dicate empty. 

RECEIVE DATA REGISTER (RDR) 

Data is automatically transferred to the empty Receive 
Data Register (RDR) from the receiver deserializer (a shift 
register) upon receiving a complete character. This event 
causes the Receive Data Register Full bit (RDRF) in the 
status buffer to go high (full). Data may then be read 
through the bus by addressing the AClAjsnd selecting the 
Receive Data Register with RS and R/W high when the 
ACIA is enabled. The non destructive read cycle causes the 
RDRF bit to be cleared to empty although the data is re- 
tained in the RDR. The status is maintained by RDRF as to 
whether or not the data is current. When the Receive Data 
Register is full, the automatic transfer of data from the 
Receiver Shift Register to the Data Register is inhibited and 
the RDR contents remain valid with its current status stored 
in the Status Register 


TABLE 1 - DEFINITION OF ACIA REGISTER CONTENTS 





Buffer Address 


Oat* 

Bus 

RS • R/W 
Transmit 

RS • R/W 
Receive 

RS • R /W 

RS • R/W 

Line 

Data 

Pata 

Control 


Number 

Register 

Register 

Register 

Register 


(Write Only) 

(Read Onlyl 

(Write Only) 

[Read Onlyl 


Daia flit 0' 

Data Bit 0 



mm 

Data Bit 1 

Oata Bit 1 


■ 

mm 

Data flit 7 

Data B>t ? 

Hnn 

Data Can ier Detect 
(D^S) 

3 

Oaia Bit 3 

Pat# B t 3 

Wont Select 7 
ICR3I 

Clear to Send 
(CTTJl 

4 

Data Bil 4 

Data Bu 4 

Word Select 3 
ICR4I 


5 

Data Bit 5 

Data Bn 5 

Transmit Control 1 
<CR5> 


6 

Data B'l 6 

Data Bit 6 



7 

Daia Bn 7 • • • 

Data Bn 7* * 


mu ESnHi m 


• UMmjl,.! tS8 B>lO 
* * Oat* hit Mill he rts'n m 7 Ixl pint iianiy mmlpj 
Om* Ini *S ilon 1 rate'* in 7 hit pint parity modes 


4-533 







MC6850* MC68A50* M C68B50 


CONTROL REGISTER 

The ACIA Control Register consists of eighty bits of write- 
only buffer that are selected when RS and R/W are low. This 
register controls the function of the receiver, transmitter, in- 
terrupt enables, and the Request-to-Send peri- 
pheral/modem control output 

Counter Divide Select Bits (CRO and CRD — The Counter 
Divide Select Bits (CRO and CR1) determine the divide ratios 
utilized in both the transmitter and receiver sections of the 
ACIA. Additionally, these bits are used to provide a master 
reset for the ACIA which clear s th e Stat us Register (except 
for external conditions on CTS and DCDI and initializes both 
the receiver and transmitter. Master reset does not affect 
other Control Register bits. Note that after power-on or a 
power fail/ restart, these bits must be set high to reset the 
ACIA. After resetting, the clock divide ratio may be selected. 
These counter select bits provide for the following clock 
divide ratios: 


CR1 

CRO 

Function 

0 

0 1 

- 1 

0 

1 

♦ 16 

1 

0 

♦64 

1 

1 

Master Reset 


Word Select Bits (CR2, CR3, end CR4) - The Word 
Select bits are used to select word length, parity, and the 
number of stop bits. The encoding format is as follows: 


CR4 

CR3 

CR2 

Function 

0 

0 

0 

7 Bits-f Even Parity 4 2 Stop Bits 

0 

0 

1 

7 Bits + Odd Parity 4-2 Stop Bits 

0 

1 

0 

7 Bits 4- Even Parity 4 1 Stop Bit 

0 

1 

f 

7 Bits 4 Odd Parity 4 1 Stop Bit 

1 

0 

0 

8 Bits 4 2 Stop Bits 

1 

0 

1 

0 $its4 1 Stop Bit 

1 

1 

0 

8 Bits 4 Even parity 4 1 Stop Bit 

1 

1 

1 

B Bits 4 Odd Parity 4 1 Stop Bit 


Word length, Parity Select, and Stop Bit changes are not 
buffered and therefore become effective immediately. 


Tranamltter Control Bit* ICR5 and CRB) - Two Transmit- 
ter Control bits provide for the control of the interrupt from 
the Tra nsm it Data Register Empty condition, the Request-to- 
Send IRtS) output, and the transmission of a Break level 
(space). The following encoding format i3 used: 


CR6 

CR6 

Function 

0 

0 

RTS = low, Transmitting Interrupt Disabled. 

0 

1 

RTS «low. Transmitting Interrupt Enabled. 

1 

0 

RTS=high, Transmitting Interrupt Disabled. 

1 

1 

RTS= iow, Transmits a Break level on the 



Transmit Data Output. Transmitting Inter- 



rupt Disabled 


Receive Interrupt Enable Bit (CR7) — The following inter- 
rupts will be enabled by a high level in bit position 7 of the 
Control Register (CR7): Receive Data Register Full, Ov errun , 
or a low- to- high transition on the Data Carrier Detect (DCD) 
signal line. 


STATUS REGISTER 

Information on the status of the ACIA is available to the 
MPU by reading the ACIA Status Register. This read-only 
register is selected when RS is low and R/W is high. Infor- 
mation stored in this register indicates the status of the 
Transmit Data Register, the Receive Data Register and error 
logic, and the peripheral/ modem status inputs of the ACIA 

Receive Data Register Full (R DR F). Bit 0 - Receive Data 
Register Full indicates that received data has been trans- 
ferred to the Receive Data Register. RDRF is cleared after an 
MPU read of the Receive Data Register or by a master reset. 
The cleared or empiy state indicates that the contents of the 
Receive Data Register are not current, Data Carrier Detect 
being high also causes RDRF to indicate empty. 

Transmit Data Register Empty ITDRE), Bit 1 - The 
Transmit Data Register Empty bit being set high indicates 
that the Transmit Data Register contents have been trans- 
ferred and that new data may be entered. The low state in- 
dicates that the register is full and that transmission of a new 
character has not begun since the last write data command. 

Data Carrier Detect IDCD), Bit 2 - The Data Carrier 
Detect bit will be high when the DCD input from a modem 
has gone high to indicate that a carrier is not present. This bit 
going high causes an Interrupt Request to be generated 
when the Rec eive Interrupt Enable is set. It remains high 
after the DCD input is returned low until cleared by first 
reading the Status Register and t hen t he Data Register or 
until a master reset occurs. If the DCD input remains high 
after read status and read d ata or master reset has occurred, 
the interrupt is clear ed, the DCD status bit remains high and 
will follow the input. 

Ctoar-to-Send I CTS), Bit 3 — The Clear- to- Send bit in- 
dicates the state of the Clear-to-Send input from a modem 
A low CTS indicates that there is a Clear to- Send from the 
modem. In the high state, the Transmit Data Register Empty 
bit is inhibited and the Clear-to-Send status bit will be high 
Master reset does not affect the Clear-to-Send status bit 

Framing Error (FE), Bit 4 — Framing error indicates that 
the received character is improperly framed by a start and a 
stop bit and is detected by the absence of the first stop bit. 
This error indicates a synchronization error, faulty transmis- 
sion, or a break condition. The framing error flag is set or 
reset during the receive data transfer time. Therefore, this er- 
ror indicator is present throughout the time that the 
associated character is available. 

Receiver Overrun IOVRN), Bit 5 — Overrun is an error flag 
that indicates that one or more characters in the data stream 
were lost. That is, a character or a number of characters 
were received but not read from the Receive Data Register 
(RDR) prior to subsequent characters being received. The 
overrun condition begins at the midpoint of the last bit of the 
second character received in succession without a read of 
the RDR having occurred. The Overrun does not occur in the 
Status Register until the valid character prior to Overrun has 


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MC6850* MC68A50* MC68B50 


been read. The RDRF bil remains set untit the Overrun is 
reset Character synchronization is maintained during the 
Overrun condition. The Overrun indication is reset after the 
reading of data from the Receive Data Register or by a 
Master Reset. 

Parity Error (PE), BK 6 — The parity error flag indicates 
that the number of highs (ones) in the character does not 
agree with the preselected odd or even parity. Odd parity is 
defined to be when the total number of ones is odd The 
parity error indication will be present as long as the data 


character is in the RDR . If no parity is selected, then both the 
transmitter parity generator output and the receiver partiy 
check results are inhibited 

Interrupt Request (?RQ), BK 7 - The IRQ bit indicates the 
State of the FEQ output. Any interrupt condition with its ap 
plicable enable will be in dicat ed in this status bit. Anytime 
the IE <3 output is low the IRQ bit will be high to indicate the 
interrupt or service request status. TrC is cleared by a read 
operation to the Receive Data Register or a write operation 
to the Transmit Data Register. 


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